1. Field of the Invention
The present invention relates to a thin film transistor (TFT). More particularly, the invention relates to a TFT of a display apparatus that reduces a leakage current caused by a hump and thus decreases a screen defect.
2. Discussion of the Related Art
An organic light emitting diode (OLED) includes an organic emission layer which is formed between two electrodes (for example, an anode electrode and a cathode electrode). An electron and a hole are injected from the two electrodes into the organic emission layer, and an exciton is generated by combining the electron with the hole. The OLED is a device using the principle that light is emitted when the generated exciton is shifted from an excited state to a ground state.
Organic light emitting display apparatuses each include a plurality of pixels which are arranged in a matrix type. In the organic light emitting display apparatus, each of the plurality of pixels includes an OLED, which emits light with a data current (Ioled) input thereto, and a pixel circuit (PC) that drives the OLED. Also, a plurality of lines for supplying a driving voltage and a signal to the OLED and the pixel circuit (PC) are provided.
The OLED and the pixel circuit are included in each of the plurality of pixels, and the OLED of each pixel emits light according to an input image signal to display an image.
Here, the pixel circuit (PC) includes a scan TFT, a sensing TFT, a driving TFT, and a storage capacitor Cst. The plurality of lines include a data line (DL), a gate line (GL), a driving power line (PL), a sensing signal line (SL), and a reference power line (RL).
FIG. 1 illustrates a gate driver that supplies a scan signal to a pixel of an organic light emitting display apparatus, and illustrates one scan circuit.
Referring to FIG. 1, the scan circuit of the gate driver generates the scan signal and supplies the scan signal to a scan TFT of a pixel circuit through a gate line.
Here, among a plurality of buffer TFTs, a pull-up TFT outputs a high voltage (a gate high voltage) to the gate line, and a pull-down TFT T1 outputs a low voltage (a gate low voltage) to the gate line. Also, a switching TFT T2 is a reset TFT that shifts a voltage, charged into a Q node, to a low voltage (for example, a ground or VGL).
When a threshold voltage (Vth) of the switching TFT T2 is lowered, an off current (Ioff) increases, and thus, a voltage of the Q node is dropped, whereby an output voltage Vgout is lowered. Also, when a threshold voltage (Vth) of the pull-down TFT T1 is lowered, an off current (Ioff) increases, and thus, the output voltage Vgout which should be output at a VGH level is lowered. Here, the output voltage Vgout denotes a high voltage that is output when the pull-up TFT is turned on.
That is, when the pull-up TFT is turned on, the output voltage Vgout should be output at the VGH level, but the output voltage Vout becomes lower than a normal voltage due to the off current (Ioff) of each of the pull-down TFT T1 and the switching TFT T2. When the output voltage Vgout of the scan circuit is lowered, a switching TFT of a pixel circuit is not normally turned on, causing a screen defect.
FIG. 2A is a diagram illustrating a plan layout of a pull-down TFT included in a scan circuit. FIG. 2B is a diagram illustrating a plan layout of a reset TFT included in the scan circuit. FIG. 2C is a diagram illustrating a plan layout of a driving TFT included in a pixel circuit. FIG. 3 illustrates a cross-sectional surface of the pull-down TFT taken along line A1-A2 of FIG. 2A, a cross-sectional surface of the reset TFT taken along line A1-A2 of FIG. 2B, and a problem where a hump occurs in the pull-down TFT and the reset TFT. The pull-down TFT and the reset TFT are formed in a coplanar top gate type. Cross-sectional surfaces of the pull-down TFT, the reset TFT, and the driving TFT are similar, and thus, the cross-sectional surface of the driving TFT is not illustrated.
As illustrated in FIG. 2A, the pull-down TFT T1 is formed to have a larger area than those of other TFTs, a gate electrode 2 is formed in a double line structure, and a multichannel is formed by overlapping of an active layer 1 and the gate electrode 2. A channel area of the active layer 1 contacts a source electrode 3 and a drain electrode 4.
As illustrated in FIG. 2B, the switching TFT T2 is formed to have a smaller area than that of the pull-down TFT T1, and a gate electrode 2 is formed in a double line structure for forming a multichannel. An active layer 1 is formed in one pattern and contacts a source electrode 3 and a drain electrode 4.
As illustrated in FIG. 2C, in the driving TFT of the pixel circuit, a gate electrode 2 is formed in a single line structure, and an active layer 1 is formed in one pattern and contacts a source electrode 3 and a drain electrode 4.
As illustrated in FIG. 3, a gate insulator 5 is formed between an active layer 1 and a gate electrode 2. Left and right edges of the active layer 1 have a taper form, and thus, a parasitic TFT is formed. That is, the taper forms of the left and right edges of the active layer 1 overlap the gate electrode 2, and thus, the parasitic TFT is formed.
In FIG. 3, although the cross-sectional surface of the driving TFT is not illustrated, identically or similarly to the pull-down TFT T1 and the switching TFT T2, left and right edges of an active layer of the driving TFT have a taper form, and thus, a parasitic TFT is formed.
A channel is formed in an area where the gate electrode 2 overlaps the active layer 1. Here, threshold voltages Vth1 and Vth3 are lower than a threshold voltage Vth2 of the channel due to the parasitic TFTs which are formed in the left and right edges of the active layer 1. When the threshold voltages Vth1 and Vth3 are lowered by the parasitic TFTs, strong electric fields are generated in the left and right edges of the active layer 1.
As shown in a transfer curve characteristic showing a shift of a drain current caused by a shift of a gate voltage, a current should linearly increase in a section of 0 V to 3 V, but since a strong electric field is generated in an edge area of an active layer, a hump where a current is nonlinearly shifted occurs. When the hump occurs, a delay of a turn-on/off time of a TFT extends, and for this reason, a switching characteristic is degraded.
As described above, a leakage current (or an off current) occurs due to humps caused by the parasitic TFTs of the left and right edges of the active layer 1, an output voltage Vgout of the scan circuit is lowered. Also, the switching TFT of the pixel circuit cannot normally operate (turn on/off), causing a screen defect.